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| IN74ACT192 PRESETTABLE BCD/DECADE UP/DOWN COUNTER High-Speed Silicon-Gate CMOS The IN74ACT192 is identical in pinout to the LS/ALS192, HC/HCT192. The IN74ACT192 may be used as a level converter for interfacing TTL or NMOS outputs to High Speed CMOS inputs. The counter has two separate clock inputs, a Count Up Clock and Count Down Clock inputs. The direction of counting is determined by which input is clocked. The outputs change state synchronous with the LOW-to-HIGH transitions on the clock inputs. This counter may be preset by entering the desired data on the P0, P1, P2, P3 input. When the Parallel Load input is taken low the data is loaded independently of either clock input. This feature allows the counters to be used as devide-by-n by modifying the count lenght with the preset inputs. In addition the counter can also be cleared. This is accomplished by inputting a high on the Master Reset input. All 4 internal stages are set to low independently of either clock input.Both a Terminal Count Down (TCD) and Terminal Count Up (TCU) Outputs are provided to enable cascading of both up and down counting functions. The TCD output produces a negative going pulse when the counter underflows and TCU outputs a pulse when the counter overflows. The counter can be cascaded by connecting the TCU and TCD outputs of one device to the Count Up Clock and Count Down Clock inputs, respectively, of the next device. * TTL/NMOS Compatible Input Levels Outputs Directly Interface to CMOS, NMOS, and TTL Operating Voltage Range: 4.5 to 5.5 V Low Input Current: 1.0 A; 0.1 A @ 25C Outputs Source/Sink 24 mA LOGIC DIAGRAM ORDERING INFORMATION IN74ACT192N Plastic IN74ACT192D SOIC TA = -40 to 85 C for all packages PIN ASSIGNMENT * * * * PIN 16 =VCC PIN 8 = GND 1 IN74ACT192 MAXIMUM RATINGS* Symbol Parameter Value Unit VCC DC Supply Voltage (Referenced to GND) -0.5 to +7.0 V VIN DC Input Voltage (Referenced to GND) -0.5 to VCC +0.5 V VOUT DC Output Voltage (Referenced to GND) -0.5 to VCC +0.5 V IIN DC Input Current, per Pin mA 20 IOUT DC Output Sink/Source Current, per Pin mA 50 ICC DC Supply Current, VCC and GND Pins mA 50 PD Power Dissipation in Still Air, Plastic DIP+ 750 mW SOIC Package+ 500 Tstg Storage Temperature -65 to +150 C 260 TL Lead Temperature, 1 mm from Case for 10 C Seconds (Plastic DIP or SOIC Package) * Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions. +Derating - Plastic DIP: - 10 mW/C from 65 to 125C SOIC Package: : - 7 mW/C from 65 to 125C RECOMMENDED OPERATING CONDITIONS Symbol Parameter VCC DC Supply Voltage (Referenced to GND) VIN, VOUT DC Input Voltage, Output Voltage (Referenced to GND) TJ Junction Temperature (PDIP) TA Operating Temperature, All Package Types IOH Output Current - High IOL Output Current - Low t r, tf Input Rise and Fall Time * VCC =4.5 V VCC =5.5 V (except Schmitt Inputs) * VIN from 0.8 V to 2.0 V Min 4.5 0 Max 5.5 VCC 140 +85 -24 24 10 8.0 Unit V V C C mA mA ns/V -40 0 0 This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, VIN and VOUT should be constrained to the range GND(VIN or VOUT)VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused outputs must be left open. 2 IN74ACT192 DC ELECTRICAL CHARACTERISTICS(Voltages Referenced to GND) Guaranteed VCC Limits Symbol Parameter Test Conditions V 25 C -40C to 85C VIH Minimum High- VOUT=0.1 V or VCC-0.1 V 4.5 2.0 2.0 Level Input 5.5 2.0 2.0 Voltage VIL Maximum Low - VOUT=0.1 V or VCC-0.1 V 4.5 0.8 0.8 Level Input 5.5 0.8 0.8 Voltage VOH Minimum High- IOUT -50 A 4.5 4.4 4.4 Level Output 5.5 5.4 5.4 Voltage * VIN=VIH or VIL 3.76 3.86 4.5 IOH=-24 mA 4.76 4.86 5.5 IOH=-24 mA VOL Maximum Low- IOUT 50 A 4.5 0.1 0.1 Level Output 5.5 0.1 0.1 Voltage * VIN=VIH 0.44 0.36 4.5 IOL=24 mA 0.44 0.36 5.5 IOL=24 mA IIN Maximum Input VIN=VCC or GND 5.5 0.1 1.0 Leakage Current VOLD=1.65 V Max IOLD +Minimum 5.5 75 Dynamic Output Current VOHD=3.85 V Min IOHD +Minimum 5.5 -75 Dynamic Output Current VIN=VCC or GND ICC Maximum 5.5 8.0 80 Quiescent Supply Current (per Package) * All outputs loaded; thresholds on input associated with output under test. +Maximum test duration 2.0 ms, one output loaded at a time. Inputs PL CPU X L H H H H X X Mode Unit V V V V A mA mA A MR H L L L L L CPD X X H H H H FUNCTION TABLE The IN74ACT192 can be preset to any state, but will not count beyond 9. If preset to state 10, 11, 12, 13, 14 or 15, it will follow the sequence 10, 11, 6: 12, 13, 4: 14, 15, 2 if Reset(Asyn.) counting Up, and follow the sequence 15, 14, Preset(Asyn.) 13, 12, 11, 10, 9 if counting Down. No Count Logic equations Count Up For Terminal Count: Count Down TC U = Q0 * Q3 * CP U No Count TC D = Q 0 * Q 1 * Q 2 * Q 3 * CP D X = don't care 3 IN74ACT192 AC ELECTRICAL CHARACTERISTICS(VCC=5.0 V 10%, CL=50pF,Input tr=tf=3.0 ns) Guaranteed Limits Unit Symbol Parameter 25 C -40C to 85C Min Max Min Max fmax Maximum Clock Frequency (Figure 1) 100 80 MHz tPLH 15 16.5 ns Propagation Delay, CPU or to TC U or TC D (Figure 2) tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPHL tPLH tPHL tPLH tPHL tPLH tPHL CIN Propagation Delay, CPU or CPD to TC U or 14 12 12 12 12 12 15 15 14 14 15 11 15 15 4.5 15.5 13.5 13.5 13.5 13.5 13.5 16.5 16.5 15.5 15.5 16.5 12.5 16.5 16.5 4.5 ns ns ns ns ns ns ns ns ns ns ns ns ns ns pF TC D (Figure 2) Propagation Delay, CPU or CPD to Qn (Figure 1) Propagation Delay, CPU or CPD to Qn (Figure 1) Propagation Delay, Pn to Qn (Figure 3) Propagation Delay, Pn to Qn (Figure 3) Propagation Delay, PL to Qn (Figure 4) Propagation Delay, PL to Qn (Figure 4) Propagation Delay, MR to Qn (Figure 5) Propagation Delay, MR to TC U (Figure 6) Propagation Delay, MR to TC D (Figure 6) Propagation Delay, PL to TC U or TC D (Figure 6) Propagation Delay, PL to TC U or TC D (Figure 6) Propagation Delay, Pn to TC U or TC D (Figure 6) Propagation Delay, Pn to TC U or TC D (Figure 6) Maximum Input Capacitance CPD Power Dissipation Capacitance Typical @25C,VCC=5.0 V 45 pF 4 IN74ACT192 TIMING REQUIREMENTS(CL=50pF, Input tr=tf=3.0 ns, VCC=5.0 V 10%) Guaranteed Limits Symbol Parameter 25 C -40C to 85C tsu 8 9 Minimum Setup Time, Pn to PL (Figure 7) th tw tw tw trec trec Minimum Hold Time, PL to Pn (Figure 7) Minimum Pulse Width, PL (Figure 4) Minimum Pulse Width, CPU or (Figure 1) Minimum Pulse Width, MR (Figure 5) CPD -1.0 14 10 12 8 14 -1.0 15 11 14 9 16 Unit ns ns ns ns ns ns ns Minimum Recovery Time, PL to CPU or CPD (Figure 5) Minimum Recovery Time, MR to CPU or CPD (Figure 5) Figure 1. Switching Waveforms Figure 2. Switching Waveforms Figure 3. Switching Waveforms Figure 4. Switching Waveforms 5 IN74ACT192 Figure 5. Switching Waveforms Figure 6. Switching Waveforms Figure 7. Switching Waveforms TIMING DIAGRAM 6 IN74ACT192 EXPANDED LOGIC DIAGRAM 7 |
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